1. Field of the Invention
The present invention relates to a power supply network analysis of a circuit device, and, more particularly, to an analysis of a power supply network of a large-scale semiconductor integrated circuit device.
2. Description of Related Art
Recently, higher performance and complexity of functions are demanded as the scale of circuits mountable in a semiconductor integrated circuit device increases in accordance with the miniaturization of the fabrication process. As a result, the scale of circuits mountable in a semiconductor integrated circuit device becomes larger and larger and the operational frequency becomes higher. To meet those demands, it becomes necessary to supply larger power source currents with the limited circuit layout area and operational timings. It is therefore important to inspect whether or not power supply lines can secure the supply of power necessary and sufficient for the individual circuit operations.
Performing this inspection is a power supply network analysis. A power supply network is an equivalent circuit which has resistors provided on power supply lines as resistor elements, has circuit elements, which consume currents, converted to current sources and has the current sources connected to connection nodes on the power supply lines to which the circuit elements are connected. Voltage values at the individual connection nodes on the power supply lines to which the circuit elements are connected and values of currents flowing across resistor elements that connect the nodes are acquired by solving the equivalent circuit. By examining the acquired voltage values and current values, it is possible to inspect whether or not the values of voltages to be supplied to the circuit elements connected to the individual nodes are fully sufficient, the currents flowing in the individual power supply lines are sufficient for the electromigration resistance and the reliability over a long operation can be guaranteed.
The following will discuss several methods that have conventionally been performed as power supply network analyses.
The first method is to replace basic elements, such as transistors, as circuit elements with current sources and extract a net list of a power supply network. This method was employed in the early stage of power supply network analysis. This method can accurately analyze a power supply network in case where the circuit scale is small.
The second method is to convert a collection of basic circuit units, such as logic gates, as a circuit cell, into a single current source. As this method can perform a power supply network analysis on the internal interconnection lines of a circuit cell without using a net list, the method is effective when adapted to a power supply network analysis on a larger circuit scale than is involved in the first method.
The third method is to omit a part of the net list of a circuit block constructed by using a plurality of circuit cells as defined in the second method and arrange the net list into a simple net list. One example of simplifying a net list using the third method is disclosed in, for example, Japanese Unexamined Patent Publication No. 2000-57186. The disclosed method comprises the step of extracting data on the widths of individual power supply terminals from layout data of a circuit block and the step of setting ratios of the individual widths to ratios of the amounts of currents consumed at the individual power supply terminals based on the data on the widths of the individual power supply terminals, and estimates the values of source currents to the individual power supply terminals from the ratios and the sum of the values of source currents to the circuit block. In other words, the third method estimates the ratios of the amounts of currents consumed at the individual power supply terminals based on layout information correlated with the amounts of source currents consumed, such as the areas of individual internal interconnection lines, the number of contacts that connect the individual internal interconnection lines to individual transistors, the areas of the contacts and the sum of the gate widths of the transistors to be connected to the individual internal interconnection lines, in addition to the widths of the individual power supply terminals. As a circuit block can be modeled by allocating current sources to the individual power supply terminals with the internal interconnection lines omitted, this method can simplify the net list.
The fourth method is to compress a net list in a circuit block leaving power supply terminals of the circuit block by using the Kirchhoff""s law. One example of compressing a net list using the fourth method is disclosed in, for example, Japanese Unexamined Patent Publication No. Hei 5-47928. The publication discloses a voltage computing method for power supply lines, which computes voltages of bending points of power supply lines and connection points from layout data of an integrated circuit that has a hierarchical design and has child cells included in a parent cell. The method prepares resistor/current source networks from the layout data of the parent cell excluding the child cells and the child cells, converts the resistor/current source network of the child cells into an equivalent circuit network equivalent to the resistor/current source network and having fewer nodes, incorporates the equivalent circuit network of the child cells into the resistor/current source network of the parent cell excluding the child cells, acquires voltage values at individual nodes in the parent cell excluding the child cells by solving a simultaneous linear equation of the resistor/current source network having voltage sources set to nodes to be connected to external units, and acquires voltage values at individual nodes in the child cells by solving a simultaneous linear equation of the resistor/current source network having voltage sources set to nodes to be connected to outside the resistor/current source network of the child cells. As solutions are obtained separately for the child cells and the parent cell excluding the child cells, the order of the simultaneous linear equation becomes smaller, thus shortening the time needed to solve the simultaneous linear equation.
According to the first method, however, as a net list is prepared by converting basic elements, such as transistors, as circuit elements to current sources and replacing portions between nodes of the power supply lines to which the current sources are connected with resistor elements included in the power supply lines, the scale of the net list becomes larger in proportion to the number of basic elements, such as transistors. The practical processing limit for the basic elements is about several tens of thousands of transistors. In case where this method is adapted to a recent large-scale integrated circuit, the analysis takes a vast amount of time using the hardware resources of an ordinary computer and may not be possible due to insufficient hardware resources, such as memory, depending on the contents of the analysis. The method therefore has such a problem that analysis cannot be executed effectively within a practical time.
While the second method can perform analysis in a larger circuit scale than the first method, it has restrictions on practical computer hardware resources in terms of the time and resources with respect to LSIs having a scale of one million logic gates, such as the recent LSIs. In consideration of the future improvement on the circuit integration, the second method will have a difficulty in analyzing a power supply network.
According to the third method, layout information, such as the widths of individual power supply terminals in a circuit block which is simplified by omitting a part of a net list has a certain correlation with the values of source currents consumed in the individual power supply terminals. However, the values of consumed source currents are settled by the circuit design, have a correlation with layout information, such as the width of the power supply terminals and the device sizes of transistors or the like, and depends on the operational ratios of the individual elements. The width of the power supply terminals and the device sizes or the like are designed with adequate margins within the range where the circuit operation can be guaranteed and the power supply terminals and circuit elements are laid out within a limited range due to the demanded high integration. That is, the widths of individual power supply terminals and the device sizes and the values of consumed source currents do not have a precise correlation with each other. As a net list is simplified by allocating current sources to individual power supply terminals by omitting interconnection lines in a circuit block to be simplified, a part of a power supply network is omitted. It is not therefore possible to accurately set the ratios of the amounts of consumed currents that are allocated to the individual power supply terminals in a circuit block to be simplified in a power supply network analysis. Further, the omission of the interconnection lines in the circuit block to be simplified actually omits a part of the power supply network, so that the analysis precision cannot be improved.
In case where the scale of the circuit to be analyzed becomes larger and the circuit scale of a child cell becomes larger, the fourth method disadvantageously takes time in the compression process for the child cells. Further, in case where the circuit scale of a child cell is large and the number of power supply terminals to be connected to a parent cell is large, the net list of the child cell, even if compressed, cannot be simplified sufficiently.
Accordingly, it is an object of the present invention to provide a power supply network analyzing method which can execute power supply network analysis of a large-scale circuit in a short period of time with fewer computer hardware resources by performing a hierarchical analysis process of compressing a part of a net list to reduce the scale of an entire net list by using the simplified net list and then analyzing a partial net list before compression based on the results of the previous analysis, and a computer program, a storage medium and a power supply network analyzing apparatus, which execute the power supply network analyzing method.
To achieve the object, according to one aspect of the present invention, there is provided a power supply network analyzing method for analyzing a characteristic of a power supply network having circuit elements to be supplied with power over power supply lines as current sources and constructed by dividing the power supply lines into resistor elements by using a net list of the power supply network, comprising a first step of converting the circuit elements to the current sources based on design information and computing the resistor elements included in the power supply lines based on physical information, thereby extracting an entire net list; a second step of selecting a portion of the power supply network which includes the current sources and in which the resistor elements are connected in series, and extracting a partial net list; a third step of acquiring a compressed net list by performing circuit compression on the partial net list; a fourth step of replacing the partial net list with the compressed net list and acquiring voltage values of individual nodes in the entire net list and current values between the individual nodes in the entire net list by applying a supply voltage to a power supply terminal in the entire net list; and a fifth step of acquiring voltage values of individual nodes in the partial net list and current values between the individual nodes in the partial net list by giving both end nodes of the partial net list to voltage values of the individual nodes in the entire net list acquired by the fourth step.
According to the power supply network analyzing method, the first step extracts an entire net list by converting the circuit elements to the current sources based on design information and computing the resistor elements included in the power supply lines based on physical information. The second step selects a portion of the power supply network which includes the current sources and in which the resistor elements are connected in series, and extracts a partial net list. The third step acquires a compressed net list by performing circuit compression on the partial net list. The fourth step replaces the partial net list with the compressed net list and acquires voltage values of individual nodes in the entire net list and current values between the individual nodes in the entire net list by applying a supply voltage to the power supply terminal in the entire net list. The fifth step acquires voltage values of individual nodes in the partial net list and current values between the individual nodes in the partial net list by giving both end nodes of the partial net list to voltage values of the individual nodes in the entire net list acquired by the fourth step.
A computer program according to another aspect of the present invention comprises a first step of replacing the circuit elements with the current sources having consumed source current values to be consumed in the circuit elements and replacing resistor components of the power supply lines with resistor elements which connect between predetermined nodes, based on input design information and physical information, thereby extracting an entire net list; a second step of selecting a portion of the power supply network which includes the current sources and in which the resistor elements are connected in series, and extracting a partial net list from the entire net list extracted in the first step; a third step of extracting a compressed net list which is the partial net list simplified; a fourth step of replacing the partial net list with the compressed net list and acquiring voltage values of the predetermined nodes and values of currents flowing in the resistor elements by analyzing the entire net list; and a fifth step of acquiring the voltage values of the predetermined nodes in the partial net list and the values of currents flowing in the resistor elements in the partial net list by giving both end nodes of the partial net list with voltage values of the predetermined nodes acquired by the fourth step.
Described in the computer program are a series of power supply network analysis procedures which allow the first step to extract an entire net list, allow the second step to extract a partial net list by selecting a portion of the power supply network which includes the current sources and in which the resistor elements are connected in series, allow the third step to extract a compressed net list which is the partial net list simplified, allow the fourth step to replace the partial net list with the compressed net list and acquire voltage values and current values, which are associated with individual predetermined nodes in the entire net list, and allow the fifth step to acquire the voltage values and current values, which are associated with individual predetermined nodes in the partial net list.
According to a further aspect of the present invention, there is provided a storage medium in which a computer readable program is stored to execute power supply network analysis for analyzing a characteristic of a power supply network having circuit elements to be supplied with power over power supply lines as current sources and constructed by dividing the power supply lines into resistor elements by using a net list of the power supply network. The program comprises a first step of converting the circuit elements to the current sources based on design information and computing the resistor elements included in the power supply lines based on physical information, thereby extracting an entire net list; a second step of extracting a partial net list of a portion of the power supply network which includes the current sources and in which the resistor elements are connected in series; a third step of acquiring a compressed net list by performing circuit compression on the partial net list; a fourth step of replacing the partial net list with the compressed net list and acquiring voltage values of individual nodes in the entire net list and current values between the individual nodes in the entire net list by applying a supply voltage to a power supply terminal in the entire net list; and a fifth step of acquiring the voltage values of the individual nodes in the partial net list and the current values between the individual nodes in the partial net list by giving both end nodes of the partial net list to voltage values of the individual nodes in the entire net list acquired by the fourth step.
Stored in the storage medium is a computer readable program for executing a series of power supply network analysis procedures which allow the first step to extract an entire net list, allow the second step to extract a partial net list, allow the third step to extract a compressed net list by performing circuit compression on the partial net list, allow the fourth step to replace the partial net list with the compressed net list and acquire voltage values at individual nodes in the entire net list and current values between the individual nodes in the entire net list, and allow the fifth step to acquire the voltage values at individual nodes in the partial net list and current values between the individual nodes in the partial net list.
With the above design, it is possible to perform a power supply network analysis on a simplified entire net list in which a partial net list is replaced with a compressed net list that has undergone circuit compression and then perform a power supply network analysis on the partial net list before compression based on the results of the previous analysis. Power supply network analysis can be carried out hierarchically by designing a hierarchical power supply network by replacing a part of an entire net list with a compressed net list that has undergone circuit compression. This can ensure a power supply network analysis of a large-scale circuit in a short period of time with fewer computer hardware resources.
Because the Kirchhoff""s law can be used in circuit compression of a partial net list, net list information will not be omitted and lost in the compressed net list. The precision of the power supply network analysis of the entire net list in which a partial net list is replaced with a compressed net list will not become lower. As the power supply network analysis of a partial net list is executed based on the results of that analysis, the precision of analysis of the partial net list will not become lower. It is possible to execute a power supply network analysis of a large-scale circuit in a short period of time with fewer computer hardware resources without lowering the analysis precision.
Because a limited portion which includes current sources and in which resistor elements are connected in series is selected as a partial net list to be compressed, circuit compression can be executed easily and the compressing process does not take time. Further, the partial net list to be selected has the number of power supply terminals to be limited to two, so that the compressed net list can be made sufficiently simple. As an entire net list replaced with a compressed net list can be simplified, it is possible to execute a power supply network analysis of a large-scale circuit in a short period of time with fewer computer hardware resources.
Here, a computer program can be provided in the form of a storage medium where the program is stored as well as can be supplied via a transmission medium, such as the Internet.
The above and further objects and novel features of the invention will more fully appear from the following detailed description when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration only and are not intended as a definition of the limits of the invention.